This invention relates generally to analog-to-digital converters, and more particularly to reduced power analog-to-digital converters.
The accuracy of an analog-to-digital (A/D) converter is dependant in part on the accuracy of op-amps used in its construction. This is particularly true in cyclic A/D converters, because they use the same op-amp throughout the entire analog-to-digital conversion process. In order to ensure the required level of accuracy from the A/D converter, conventional cyclical A/D converters are designed to maintain the op-amp at the highest level of accuracy, usually better than one least- significant bit (LSB), during the entire analog-to-digital conversion process.
In general, when an op-amp is operated to achieve a high level of accuracy, a relatively large amount of power is consumed. Conversely, when relatively low accuracy is required of an op-amp, a lower amount of power is required. As a result, although operating the op-amp in an A/D converter at a high level of accuracy results in an accurate output from the A/D converter, the accuracy comes at the cost of high power consumption. This high power consumption can be problematic when A/D converters are used in limited-power applications, such as wireless phones and other portable devices. At the very least, a reduction in the power needed to operate the op-amp of an A/D converter could make more power available for use by other circuitry.
What is needed, therefore, is a way to decrease the amount of power used by an op-amp of an A/D converter, without sacrificing the overall accuracy of the A/D converter.